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PRELIMINARY TECHNICAL DATA
a
Thermoelectric Cooler Controller Preliminary Technical Data ADN8830
FEATURES High Efficiency Small Size: 5 mm 5 mm LFCSP Low Noise: < 0.5% TEC Current Ripple Long Term Temperature Stability: 0.01 C Frequency and Phase Compensation in Control Loop Temperature Lock Indication Thermistor Linearity Correction Compatibility Temperature Monitoring Output Oscillator Synchronization with an External Signal Clock Phase Adjustment for Multiple Controllers Programmable Switching Frequency up to 1 MHz Thermistor Failure Alarm Maximum TEC Voltage Programmability APPLICATIONS Thermoelectric Cooler (TEC) Temperature Control Resistive Heating Element Control Temperature-Stabilization Substrate (TSS) Control GENERAL DESCRIPTION
The ADN8830 is a monolithic controller that drives a Thermoelectric Cooler (TEC) to stabilize the temperature of a laser diode or a passive component used in telecommunications equipment. This device relies on a Negative Temperature Coefficient (NTC) thermistor to sense the temperature of the object attached to the TEC. The target temperature is set with an analog input voltage either from a DAC or with an external resistor divider.
The loop is stabilized by a PID compensation amplifier with high stability and low noise. The compensation network can be adjusted by the user to optimize temperature settling time. The component values for this network can be calculated based on the thermal transfer function of the laser diode or obtained from the look-up table given in the applications notes. Voltage outputs are provided to monitor both the temperature of the object and the voltage across the TEC. A 2.5 V voltage reference is also provided.
FUNCTIONAL BLOCK DIAGRAM
PID COMPENSATION NETWORK
FROM THERMISTOR TEMP SET INPUT
P-CHANNEL (UPPER MOSFET) TEMPERATURE MEASUREMENT AMPLIFIER PWM CONTROLLER MOSFET DRIVERS P-CHANNEL (LOWER MOSFET) N-CHANNEL N-CHANNEL
VREF
VOLTAGE REFERENCE
OSCILLATOR
FREQUENCY/PHASE CONTROL
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADN8830-SPECIFICATIONS configuration as shown in Figure 1, unless otherwise noted.)
Parameter TEMPERATURE STABILITY Long Term Stability PWM OUTPUT DRIVERS Output Transition Time Non-Overlapping Clock Delay Maximum Gate Drive Current Output Resistance Output Voltage Swing Output Voltage Ripple Output Current Ripple LINEAR OUTPUT AMPLIFIER Capacitive Load Drive Output Resistance Output Voltage Swing POWER SUPPLY Power Supply Voltage Power Supply Rejection Ratio Supply Current Shutdown Current Soft-Start Charging Current Undervoltage Lockout ERROR AMPLIFIER Input Offset Voltage Gain Input Voltage Range Common-Mode Rejection Ratio Open-Loop Input Impedance Gain-Bandwidth Product REFERENCE VOLTAGE Reference Voltage OSCILLATOR Sync Range Oscillator Frequency Phase Adjustment LOGIC CONTROL1 Logic Low Input Threshold Logic High Input Threshold Logic Low Output Level Logic High Output Threshold
NOTE 1 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 A).
(@ VDD = 3.3 V to 5.0 V, VGND = 0 V, TA =
25 C, TSET = 25 C, using typical application
Symbol
Conditions Using 10 k thermistor with, = -4.4% at 25C
Min
Typ
Max
Units
0.01 20 65 1.0 6 0 0.2 0.2 10 VDD
C ns ns A V % % nF V V dB mA mA A A V V V/V V dB dB G MHz V kHz kHz Degrees V V V V
t R , tF IMAX(N1,P1) RO(N1,P1) OUTA OUTA ITEC CLOAD(N2, P2) R0, P2 R0, N2 OUTB VDD PSRR ISY ISD ISS VOLOCK VOS AV, IN VCM CMRR RIN GBW VREF fCLK fCLK CLK
CL = 3,300 pF IL = 50 mA VLIM = 0 V fCLK = 1 MHz fCLK = 1 MHz
IOUT = 2 mA IOUT = 2 mA 0 3.3 60 50
85 178 VDD 5.0 92 8 5 100 2.6 50 20 0.2 68 60 1.0 2 12 150
VDD = 3.3 V to 5 V, VTEC = 0 V -40C TA +85C PWM not switching -40C TA +85C Pin 10 = 0 V Low to high threshold VCM = 1.5 V 0.2 V < VCM < 2.0 V -40C TA +85C
2.7 250 2.0
IREF < 2 mA Pin 25 connected to external clock Pin 24 = VDD; (R = 300 k; Pin 25 = GND)
2.45 200 480 45
2.47
2.49 1,000
500
520 360 0.2
3.0 0.2 VDD - 0.2
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PRELIMINARY TECHNICAL DATA ADN8830
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to VS +0.3 V Output Short Circuit to GND Duration . . . . . . . . . . . . . TBD Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Junction Temperature Range CP Packages . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300C
ESD RATINGS
Package Type 32-Lead LFCSP (ACP)
1 JA
JC
Units C/W
35
10
NOTE 1 JA is specified for worst case conditions, i.e., JA is specified for device soldered in 4-layer circuit board for surface mount packages.
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.0 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Model ADN8830ACP
Package Range -40C to +85C
Package Description 32 -Lead Chip Scale Micro-Lead Frame LFCSP
PIN CONFIGURATION
32 NC 31 TEMPOUT 30 AGND 29 PHASE 28 SYNCOUT 27 SOFTSTART 26 FREQ 25 SYNCIN
Package Option CP-32
Branding Information
THERMFAULT 1 THERMIN 2 SD 3 TEMPSET 4 TEMPLOCK 5 NC 6 VREF 7 AVDD 8
PIN 1 INDICATOR
ADN8830
TOP VIEW
24 COMPOSC 23 PGND 22 N1 21 P1 20 PVDD 19 OUT A 18 COMPSWIN 17 COMPSWOUT
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
OUT B 9 N2 10 P2 11 TEMPCTL 12 COMPFB 13 COMPOUT 14 VLIM 15 VTEC 16
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA ADN8830
Table I. ADN8830 Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Name THERMFAULT THERMIN SD TEMPSET TEMPLOCK NC VREF AVDD OUT B N2 P2 TEMPCTL COMPFB COMPOUT VLIM VTEC COMPSWOUT COMPSWIN OUT A PVDD P1 N1 PGND COMPOSC SYNCIN FREQ SOFTSTART SYNCOUT PHASE AGND TEMPOUT NC
Type Digital Output Analog Input Digital Input Analog Input Digital Output
Description Indicates an open or short-circuit condition from thermistor. Thermistor feedback input. Puts device into low current shutdown mode. Active low. Target temperature input. Indicates when thermistor temperature is within 0.1C of target temperature as set by TEMPSET voltage. No connection, except as noted in applications note. 2.5 V reference voltage. Power for non-driver sections. 3.3 V min; 5 V max. Linear output feedback. Will typically connect to TEC+ pin of TEC. Drives linear output external NMOS gate. Drives linear output external PMOS gate. Output of error amplifier. Connects to COMPFB through feedforward section of compensation network. Feedback summing node of compensation amplifier. Connects to TEMPCTL and COMPOUT through compensation network. Output of compensation amplifier. Connects to COMPFB through feedback section of compensation network. Sets maximum voltage across TEC. Indicates relative voltage across the TEC. 1.5 V corresponds to 0 V across TEC. 3.0 V indicates maximum output voltage, maximum heat transfer through TEC. Compensation for switching amplifier. Compensation for switching amplifier. Capacitor connected between COMPSWIN and COMPSWOUT. PWM output feedback. Will typically connect to TEC- pin of TEC. Power for output driver sections. 3.3 V min; 5 V max. Drives PWM output external PMOS gate. Drives PWM output external NMOS gate. Power ground. External NMOS devices connect to PGND. Can be connected to digital ground as noise sensitivity at this node is not critical. Connect as indicated in applications note. Optional clock input. If not connected, clock frequency set by FREQ pin. Sets switching frequency. Controls initialization time for ADN8830 with capacitor to ground. Phase adjusted clock output. Phase set from PHASE pin. Can be used to drive SYNCIN of other ADN8830 devices. Sets switching and SYNCOUT clock phase relative to SYNCIN clock. Analog ground. Should be low noise for highest accuracy. Indication of thermistor temperature. No connection.
Analog Output Power Analog Input Analog Output Analog Output Analog Output Analog Input Analog Output Analog Input Analog Output Analog Output Analog Input Analog Input Power Digital Output Digital Output Ground Analog Input Digital Input Analog Input Analog Input Digital Output Analog Input Ground Analog Output
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PRELIMINARY TECHNICAL DATA ADN8830
APPLICATIONS NOTES Principle of Operation
The ADN8830 is a controller for a Thermoelectric Cooler (TEC) and is used to set and stabilize the temperature of the TEC. A voltage applied to the input of the ADN8830 corresponds to a target temperature set point. The appropriate current is then applied to the TEC to either pump heat to or away from the object whose temperature is being regulated. The temperature of the object is measured by a thermistor and is fed back to the ADN8830 to correct the loop and settle the TEC to the appropriate final temperature. For best stability, the thermistor should be mounted in close proximity to the object. In most laser diode modules, the TEC and thermistor are already mounted in the unit and are used to regulate the temperature of the laser diode. For a TEC controller to provide a complete solution it requires a precision input amplifier stage to accurately measure the difference between the target temperature and the actual temperature of the object, a compensation amplifier to optimize the temperature step response of the TEC, and a high output current stage
to provide the required current to the TEC. Because of the high output currents involved, a TEC controller should operate with high efficiency to minimize the heat generated from power dissipation. In addition, an effective controller should operate down to +3.3 V and have an indication of when the target temperature has been reached. The ADN8830 accomplishes all of these requirements with a minimum of external components. Figure 1 shows a reference design for a typical application. Temperature is monitored by connecting the measurement thermistor to a precision amplifier, called the error amplifier, with a simple resistor divider. This voltage is compared against the temperature set input voltage creating an error voltage that is proportional to their difference. To maintain accurate wavelength and power from the laser diode, this difference voltage must be as accurate as possible. For this reason self correction auto-zero amplifiers are used in the input stage of the ADN8830, providing a maximum offset voltage of 250 V over time and temperature. This results in final temperature accuracy within 0.01C in typical applications, eliminating the ADN8830 as an error source in the temperature control loop. A logic output is
SYNCOUT TEMPOUT C1 0.1 F R1 150k
32 THERMFAULT 1
31
30
29
28
27
26
25 24
3.3V
L1 4.7 H COILCRAFT DO3316-472 TEC-
THERMIN RTH 10k @25 C
R2 7.68k 0.1% VREF
2
23 Q1 FDW2520C-B
C2 22 F CDE ESRD
3 3.3V TEMPSET R3 10k 0.1% 4
22
21
Q2 FDW2520C-A
ADN8830
5 20 C3 10 F 6 19 C4 22 F CDE ESRD 3.3V
TEMPLOCK R4 7.68k 0.1%
3.3V
VREF
7
18 C5 10nF
3.3V C8 10 F
8 9 10 11 12 R5 205k C11 1F 13 C9 10 F R6 100k C10 330pF VTEC 14 15 16
17
3.3V C7 10 F
Q3 FDW2520C-A C6 2.2nF TEC+ Q4 FDW2520C-B C12 3.3nF
R7 1M
Figure 1. ADN8830 Typical Application Schematic
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PRELIMINARY TECHNICAL DATA ADN8830
provided at TEMPLOCK to indicate when the target temperature has been reached. The output of the error amplifier is then fed into a compensation amplifier. An external network consisting of a few resistors and capacitors is connected around the compensation amplifier. This network can be adjusted by the user to optimize the step response of the TEC's temperature either in terms of settling time or maximum current change. Details of how to adjust the compensation network are given in the application notes. The ADN8830 can be easily integrated with a wavelength locker for fine-tune temperature adjustment of the laser diode for a specific wavelength. This is a useful topology for tunable wavelength lasers. Details are highlighted in the applications section. The TEC is driven differentially using an H-bridge configuration to maximize the output voltage swing. The ADN8830 drives external transistors which are used to provide current to the TEC. These transistors can be selected by the user based on the maximum output current required for the TEC. The maximum voltage across the TEC can be set through use of the VLIM pin on the ADN8830. To further improve the power efficiency of the system, one side of the H-bridge uses a switched output. Only one inductor and one capacitor are required to filter out the switching frequency. The output voltage ripple is a function of the output inductor and capacitor and the switching frequency. For most applications, a 4.7 H inductor, 22 F capacitor, and switching frequency of 1 MHz maintains less than 0.5% worst case output voltage ripple across the TEC. The other side of the H-bridge does not require any additional circuitry. The oscillator section of the ADN8830 controls the switched output section. A single resistor sets the switching frequency from 100 kHz to 1 MHz. The clock output is available at the SYNCOUT pin and can be used to drive another ADN8830 device by connecting to its SYNCIN pin. The phase of the clock is adjusted by a voltage applied to the PHASE pin, which can be set by a simple resistor divider. Phase adjustment allows two or more ADN8830 devices to operate from the same clock frequency and not have all outputs switch simultaneously, which could create an excessive power supply ripple. Details of how to adjust the clock frequency and phase are given in the applications section of the datasheet. For effective indication of a catastrophic system failure, the ADN8830 alerts to open-circuit or short-circuit condition from the thermistor, preventing an erroneous and potentially damaging temperature correction from occurring. With some additional external circuitry, output over-current detection can be implemented to provide warning in the event of a TEC short circuit failure. This circuit is highlighted in the application notes.
Signal Flow Diagram
The voltage at TEMPCTL is then fed into the compensation amplifier whose frequency response is dictated by the compensation network. Details on the compensation amplifier can be found in the Compensation Loop section. When configured as a simple integrator or PID loop, the DC forward gain of the compensation section is equal to the open loop gain of the compensation amplifier, which is over 80 dB or 10,000. The output from the compensation loop at COMPOUT is then fed to the linear amplifier. The output of the linear amplifier at OUT_B is fed with COMPOUT into the PWM amplifier whose output is OUT_A. These two outputs provide the voltage drive directly to the TEC. Including the external transistors, the gain of the differential output section is fixed at 4. Details on the output amplifiers can be found in the Output Driver Amplifiers section of the application notes.
1.5V 4 TEMPSET THERMIN 2 INPUT AMPLIFIER 1.5V AV = 20 9 AV = Z2/Z1 12 Z1 13 Z2 AV = 4 14 COMPENSATION PWM/LINEAR AMPLIFIER AMPLIFIERS 19 OUT A OUT B
Figure 24. Signal Flow Block Diagram of ADN8830
Thermistor Setup
The temperature of the thermal object, such as a laser diode, is detected with a negative temperature coefficient (NTC) thermistor. The thermistor's resistance exhibits an exponential relationship to the inverse of temperature, meaning the resistance decreases at higher temperatures. Thus, by measuring the thermistor resistance, temperature can be ascertained. For this application, the resistance is measured using a voltage divider. The thermistor is connected between THERMIN and AGND, Pins 7 and 30, respectively. Another resistor (RX) is connected between VREF and THERMIN, Pins 7 and 2, creating a voltage divider for the VREF voltage. Figure 2 shows the schematic for this configuration.
VDD 8 7 RX 2
ADN8830
RTHERM 30
Figure A24 shows the signal flow diagram through the ADN8830. The input amplifier is fixed with a gain of 20. The voltage at TEMPCTL can be expressed as: TEMPCTL = 20 x (TEMPSET - THERMIN ) + 1.5 (0)
Figure 2. Connecting a Thermistor to the ADN8830
When the temperature is settled, the thermistor voltage will be equal to the TEMPSET voltage and the output of the input amplifier will be 1.5 V.
With the thermistor connected from THERMIN to AGND, the voltage at THERMIN will decrease as temperature increases. To maintain the proper input to output polarity in this configuration, Pin 19, OUT_A, should connect to the TEC- pin on the TEC and Pin 9, OUT_B, should connect to TEC+.
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PRELIMINARY TECHNICAL DATA ADN8830
The thermistor can also be set up connected from VREF to THERMIN with RX connecting to ground. In this case, OUT_A must connect to TEC+ with OUT_B connected to TEC- for proper operation. Although the thermistor has a non-linear relationship to temperature, near optimal linearity over a specified temperature range can be achieved with the proper value of RX. First, the resistance of the thermistor must be known, where: RTHERM = RT 1 @ T = TLOW = RT 2 @ T = TMID = RT 3 @ T = THIGH (1) VX for high, mid, and low are found by using Equation 5 and substituting RT3, RT2, and RT1 respectively for RTHERM. The variable m is the change in VX with respect to temperature and is expressed in V/C. The set point voltage can be driven from a D/A converter, or another voltage source as shown in Figure 3. The reference voltage for the DAC should be connected to the VREF pin on the ADN8830 (Pin 7) to ensure best accuracy from device to device. For a fixed target temperature, a voltage divider network can be used as shown in Figure 4. R1 is set equal to RX and R2 is equal to the value of RTHERM at the target temperature.
3.3V 7 1-4 3.3V 8 6 4
TLOW and THIGH are the end points of the temperature range and TMID is the average. These resistances can be found in most thermistor datasheets. In some cases, only the coefficients corresponding to the Steinhart-Hart equation are given. The Steinhart-Hart equation is: 1 = a + b1n(R ) + c 1n(R ) T
AD7390
5 8
[
]
3
ADN8830
7
(2)
C
Where T is the absolute temperature of the thermistor in Kelvin (K = C + 273.15), and R is the resistance of the thermistor at that temperature. Based on the coefficients a, b, and c, RTHERM can be calculated for a given T, albeit somewhat tediously, by solving the cubic roots of this equation:
1 1 1 3 1 3 2 3 2 2 3 2 + - - + = exp - + + 2 4 27 2 4 27 (3)
30
Figure 3. Using a DAC to Control the Temperature Set Point
3.3V 8 7 R1 4
RTHERM
ADN8830
Where, =
a-
1 b T , and = c c
R2 30
RX is then found as:
RX = RT 1RT 2 + RT 2RT 3 - 2RT 1RT 3 RT 1 + RT 3 - 2RT 2
Figure 4. Using a Voltage Divider to Set a Fixed Temperature Set Point
(4)
Design Example 1:
For best accuracy as well as the widest selection range for resistances, RX should be 0.1% tolerance. Naturally, the smaller the temperature range required for control, the more linear the voltage divider will be with respect to temperature. The voltage at THERMIN is:
VX = VREF RTHERM RTHERM + RX
A laser module requires a constant temperature of 25C. From the manufacturer's datasheet, we find the thermistor in the laser module has a value of 10 k at 25C. Because the laser in not required to operate at a range of temperatures, the value of RX can be set to 10 k. TEMPSET can be set by a simple resistor divider as shown in Figure 4 with R1 and R2 both equal to 10 k.
Design Example 2:
(5)
Where VREF has a typical value of 2.47 V. The ADN8830 control loop will adjust the temperature of the TEC until VX equals the voltage at TEMPSET (Pin 4), which we define as VSET. Target temperature can be set by: VSET = m (T - TMID ) + VXMID Where, T equals the target temperature, and m= REV. PrC VX , HIGH - VX , LOW THIGH - TLOW (7) (6)
A laser module requires a continuous temperature control from 5C to 45C. The manufacturer's datasheet shows the thermistor has a value of 10 k at 25C, 25.4 k at 5C, and 4.37 k at 45C. Using equation 4, RX is calculated to be 7.68 k to yield the most linear temperature-to-voltage conversion. A D/A converter will be used to set the TEMPSET voltage.
DAC Resolution for TEMPSET
The temperature set point voltage to THERMIN can be set from a D/A converter. The DAC must have a sufficient number of bits to achieve adequate temperature resolution from the system. The voltage range for THERMIN is found by multiplying the variable m from Equation 7 by the temperature range. -7-
PRELIMINARY TECHNICAL DATA ADN8830
THERMIN Voltage Range = m x (TMAX - TMIN ) From Design Example 2 above, 40C of control temperature range is achieved with a voltage range of only 1 V. To eliminate the resolution of the DAC as the principle source of system error, the step size of each bit, VSTEP, should be lower than the desired system resolution. A practical value for absolute DAC resolution is the equivalent of 0.05C. The value of VSTEP should be less than the value of m from Equation 7 multiplied by the desired temperature resolution, or VSTEP < 0.05o C x m (9)
RFREQ =
(8) fSWITCH 100 kHz 250 kHz 500 kHz 750 kHz 1 MHz
Table I. Switching Frequencies vs. RFREQ
RFREQ 1.5 M 600 k 300 k 200 k 150 k
For other frequencies, the value for this resistor, RFREQ, should be set to:
150 x 109 f SWITCH
Where, m is the slope of the voltage-to-temperature conversion line, as found from Equation 6. From Design Example 2, where m = 25 mV/C, we see the DAC should have resolution better than 1.25 mV per step. The minimum number of bits required is then given as:
# of bits = log (VFS ) - log (VSTEP ) log (2)
(11)
Where fSWITCH is the switching frequency in Hz. Highger switching frequencies reduce the voltage ripple across the TEC. However, high switch frequencies will create more power dissipation in the external transistors. This is due to the more frequent charging and discharging of the transistors' gate capacitances. If large transistors are needed for a high output current application, faster switching frequencies could reduce the overall power efficiency of the circuit. This is covered in detail in the Switched Output section of the application notes. The switching frequency of the ADN8830 can be synchronized with an external clock by connecting the clock signal to Pin 25, SYNCIN. Pin 24 should also be connected to an R-C network as shown in Figure 11A. This network is simply used to compensate a PLL to lock on to the external clock. To ensure the quickest synchronization lock-in time, RFREQ should be set to 1.5 M.
1nF COMPOSC 24 1k 0.1 F
(10)
Where, VFS is the full scale output voltage from the DAC, which should be equal to the reference voltage from the ADN8830, VREF = 2.45 V as given in the specifications data for the reference voltage. In this example, the minimum resolution is 11 bits. A 12-bit DAC can be readily found, such as the AD7390. It is important that the full scale voltage input to the DAC is tied to the ADN8830 reference voltage as shown in Figure 2. This eliminates errors from slight variances of VREF from different ADN8830 devices.
Thermistor Fault and Temperature Lock Indications
Both the THERMFAULT and TEMPLOCK outputs at pins 1 and 5 respectively are CMOS compatible outputs that are active high. THERMFAULT will be a logic low while the thermistor is operating normally and will go to a logic high if a short or open is detected at THERMIN, pin 2. The trip voltage for THERMFAULT is when THERMIN falls below 0.2 V or exceeds 2.0 V. THERMFAULT only provides an indication of a fault condition and does not activate any shutdown or protection circuitry on the ADN8830. To shutdown the ADN8830 a logic low voltage must be asserted on pin 3 as described in the Shutdown Mode section of the datasheet. TEMPLOCK will output a logic high when the voltage at THERMIN is within 2.5 mV of TEMPSET. This voltage can be related to temperature by solving for m from Equation 7. For most laser diode applications, 2.5 mV is equivalent to 0.1C. If the voltage difference between THERMIN and TEMPSET is greater than 2.5 mV then TEMPLOCK will output a logic low. The input offset voltage of the ADN8830 is guaranteed to within 250 mV which for most applications is within 0.01C.
Setting the Switching Frequency
ADN8830
FREQ
26
1.5M
Figure 11. Using an R-C Network on Pin 24 with an External Clock
The relative phase of the ADN8830 internal oscillator compared to the external clock signal can be adjusted. This is accomplished by adjusting the voltage to Pin 29, the PHASE pin according to Figures XX and XX. The phase shift versus voltage can be approximated as:
Phase shift = 360 x
VPHASE VREF
(12)
Where, VPHASE is the voltage at Pin 29, and VREF has a typical value of 2.47 V. To ensure the oscillator operates correctly, VPHASE should remain higher than 100 mV and lower than 2.3 V. This is required for either internal clock or external sync operation. A resistor divider from VREF to ground can establish this voltage easily, although any voltage source, such as a DAC, could be used as well. If phase is not a consideration, for example with a single
The ADN8830 has an internal oscillator to generate the switching frequency for the output stage. This oscillator can be either set in free-run mode or synchronized to an external clock signal. For free-run operation, Pin 25 (SYNCIN) should be connected to ground and Pin 24 (COMPOSC) should be connected to AVDD. The switching frequency is then set by a single resistor connected from Pin 26 (FREQ) to ground. Table 1 shows some values for RFREQ to obtain a desired switching frequency. -8-
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PRELIMINARY TECHNICAL DATA ADN8830
ADN8830 being used, then Pin 29 can be tied to Pin 6, which provides a 1.5 V reference voltage. The phase adjusted output from the ADN8830 is available at Pin 28, SYNCOUT. This pin can be used as a master clock signal for driving other ADN8830 devices. Multiple ADN8830 devices can be either driven from a single master ADN8830 device by connecting its SYNCOUT pin to each slave's SYNCIN pin, or daisy-chained by connecting each device's SYNCOUT to the next device's SYNCIN pin. Phase shifting is useful in systems that use more than one ADN8830 TEC controller. It ensures the ADN8830 devices will not all switch at the same time, which could create too much ripple on the power supply voltage. By adjusting the phase of each device, the switching can be spread out equally over the clock period, reducing potential supply ripple and easing the instantaneous current demand from the supply. Using a single master clock, each slave ADN8830 should have a different value phase shift. For example, with four TEC controllers, one slave device should be set for 90 of phase shift, another for 180, and the last slave for 270. In a daisy-chain configuration, each slave device would be set with equal phase. Using the previous example, each slave would be set to 90 with its SYNCOUT pin connected to the next device's SYNCIN pin. Examples are shown in Figures A5 and A6.
ADN8830 SLAVE
29 150k VDD 24 25 26 1.5M
Soft Start on Power Up
The ADN8830 can be programmed to ramp up for a specified time after the power supply is applied or after shutdown is de-asserted. This feature, known as soft start, is useful for gradually increasing the duty cycle of the PWM amplifier. The soft start time is set with a single capacitor connected from Pin 27 to ground according to Equation 13:
SS = 150 x C SS
(13)
Where, CSS is the value of the capacitor in microfarads, and tSS is the soft start time in milliseconds. To set a soft start time of 15 ms, CSS should equal 0.1 F. A minimum soft start time of 10 ms is recommended to ensure proper initialization of the ADN8830 on power up.
Shutdown Mode
The ADN8830 has a shutdown mode which deactivates the output stage and puts the device into a low current standby state. The current draw for the ADN8830 in shutdown is less than 100 A. The shutdown input, Pin 3, is active low. To shut the device down, Pin 3 should be driven to logic low. Once a logic high is applied, the ADN8830 will reactivate after the delay set by the soft start circuitry. Refer to the Soft Start on Power Up section for more details on this feature. Pin 3 should not be left floating as there are no internal pull-up or pull-down resistors. If the shutdown function is not required, Pin 3 should be tied to VDD to ensure the device is always active.
Compensation Loop
25 7 50k
28 24
NC
1k
1nF
0.1 F
ADN8830 MASTER
29 26
28
25 7 100k
ADN8830 SLAVE
29 26
28 24
NC
6 RFREQ
1k
1nF
0.1 F 100k 1.5M
The ADN8830 TEC controller has a built-in amplifier dedicated for loop compensation. The exact compensation network is set by the user and can vary from a simple integrator, to PI, PID, or any other type of network. The type of compensation and component values should be determined by the user as it will depend on the thermal response of the object and the TEC. One method for determining these values empirically is to input a step function to TEMPSET, thus changing the target temperature, and adjusting the compensation network to minimize the settling time of the object's temperature. A typical compensation network used for temperature control of a laser module is a PID loop, which consists of a very low frequency pole and two separate zeros at higher frequencies. Figure 7 shows a simple network for implementing PID compensation. An additional pole is added at a higher frequency than the zeros to reduce the noise sensitivity of the control loop. The bode plot of the magnitude is shown in Figure 8. The unity-gain crossover frequency of the feed forward amplifier is given as:
25 7 150k
ADN8830 SLAVE
29 26
28 24
NC
1k
1nF
0.1 F 50k 1.5M
Figure 5. Multiple ADN8830 Devices Driven from a Master Clock
1nF VDD 24 25 0.1 F 1k 24 28 0.1 F 1k 24 28 0.1 F 1k 24 28 1nF 1nF
NC
ADN8830 MASTER
29 26
28
25 7 150k
ADN8830 SLAVE
29 26
25 7 150k
ADN8830 SLAVE
29 26
25 7 150k
ADN8830 SLAVE
29 26
NC
6 RFREQ
49.9k
1.5M
50k
1.5M
50k
1.5M
Figure 6. Multiple ADN8830 Devices Using a Daisy-Chain
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PRELIMINARY TECHNICAL DATA ADN8830
f0dB = 1 x 80 x TEC GAIN 2R 3C1 (14)
ADN8830
To ensure stability, the unity-gain crossover frequency should be lower than the thermal time constant of the TEC and thermistor. However, this thermal time constant may not be specified and can be difficult to characterize. There are many texts written on loop stabilization and it is beyond the scope of this datasheet to discuss all methods and trade-offs in optimizing compensation networks. A simple method that can be used to empirically determine a PID compensation loop as shown in Figure A7 involves the following procedure: 1. Connect thermistor and TEC to ADN8830 application circuit. Power does not need to be applied to the laser diode for this procedure. Monitor output voltage across the TEC with an oscilloscope. 2. Short C1 and open C2, leaving just R1 and R3 as a simple proportional-only compensation loop. 3. While maintaining a constant TEMPSET voltage, increase the ratio of R1/R3 thus increasing the gain until loop oscillation starts to occur. Decrease this ratio by a factor of 2 from the point of oscillation. The R1/R3 ratio will likely be less than unity for most laser modules. 4. Add C1 capacitor and decrease value until oscillation starts, then increase by a factor of 2. A good initial starting value for C1 is to create a unity-gain crossover of 0.1 Hz based on Equation 14. 5. Short R2 and increase C2 until oscillation starts. At this point, either C2 can be decreased or R2 can be added to regain stability. Generally speaking, R2 will be greater than R3 and C2 will be one or more orders of magnitude less than C1. 6. TEMPSET should be adjusted with a step change while observing the output voltage settling time. A step change of 100 mV should suffice. From here, C2, R2 and even C1 can be decreased to minimize settling time at the expense of additional output voltage overshoot. 7. An additional feedback capacitor in parallel with R1 and C1 can be added to add another high frequency pole. In many cases, this improves the stability of the system without increasing settling time as out-of-band noise is filtered out of the control signal. A 330 pF to 1 nF capacitor should suffice, if required. The typical values shown in typical application circuit in Figure 1 have R1 = 100 k, R2 = 1 M, R3 = 205 k, C1 = 10 F, C2 = 1 F, and an additional feedback capacitor of 330 pF. For most pump laser modules, this results in a 10C TEMPSET step settling time to within 0.1C in less than 5 seconds.
REFERENCE VOLTAGE COMPOUT TEMPCTL 12 R3 R1 R2 C2 C1 COMPFB 13 14
Figure 7. Implementing a PID Compensation Loop
MAGNITUDE - LOG SCALE
0dB
R1 R2||R3
R1 R3
1 2 R3C1
1 1 2 R1C1 2 C2(R2+R3) FREQUENCY - Hz LOG SCALE
1 2 R2C2
Figure 8. Bode Plot for PID Compensation
Using TEC Controller ADN8830 with a Wave Locker
Many optical applications require precision control of laser wavelength. The wavelength of the laser diode can be adjusted by adjusting its temperature, which is done through temperature control of the TEC. Wavelength control can be done by feeding a wave locker or etalon output back to the microprocessor and using the microprocessor to calculate and re-instruct the TEC controller with a new target temperature. However, this method is computationally expensive and has time delays before the adjustment is done. A faster responding and simpler method is to feed the wave locker signal back to the TEC controller for direct temperature control. The ADN8830 is designed to be compatible with a wave locker controller. Figure 9 shows the basic schematic. The TEMPCTL output from ADN8830 is proportional to the object's actual temperature. This voltage is fed to the wave locker controller. Also fed to the wave locker controller are the photodiode outputs from the wave locker, as well as the laser diode power and a digital signal indicating a functional laser diode, both of which come from the CW controller. The output of the wave locker controller is then connected to the input of the compensation network. This allows the wave locker controller to adjust the TEC temperature based on the current temperature of the object, the current wavelength of the laser diode, and the target wavelength. Once the target wavelength is reached, the wave locker
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PRELIMINARY TECHNICAL DATA ADN8830
controller sends a signal to the micro-controller indicating the laser signal is good.
LOCKER PD1 VTEC, MAX - V LOCKER PD2 WAVE LOCKER GOOD FROM CW CONTROLLER LASER DIODE POWER LASER DIODE GOOD TEC CONTROL TEMP IN 3 5 4 FROM LOCKER
ADN8830
TO MICROPROCESSOR
2
1
TEMPCTL COMPFB 13 COMPOUT 14
12
0
0
0.5
1.0 VLIM - V
1.5
2.0
COMPENSATION NETWORK
Figure A10: Graph of VLIM Voltage vs. Maximum TEC Voltage
Figure 9. Using the ADN8830 with a Wave Locker
Using TEMPOUT to Measure Temperature
The TEMPOUT pin is a voltage that is proportional to difference between the target temperature and the measured thermistor temperature. The full equation for the voltage at TEMPOUT is: TEMPOUT = 1.5 + 3 x (THERMIN - TEMPSET ) (16) The voltage range of TEMPOUT is 0 V to 3.0 V and is independent of power supply voltage.
Setting the Maximum TEC Voltage and Current
If the supply voltage is lower than VTEC,MAX, then the maximum TEC voltage will obviously be equal to the supply voltage. The voltage to VLIM should not exceed 1.5 V as this causes improper operation of the output voltage limiting circuitry. Setting VLIM to 1.5 V can be used to deactivate the TEC current without shutting down the ADN8830 in the event of a system failure. If a maximum TEC voltage is not required, then VLIM should be connected to ground. It is not advisable to leave VLIM floating as this would cause unpredictable output behavior. This feature should be used to limit the maximum output current to the TEC as specified in the TEC datasheet. For example, if the maximum TEC voltage is specified at 2 V, then VLIM should be set to 1 V. The maximum output voltage is then set to 2 V.
Output Driver Amplifiers
The ADN8830 can be programmed for a maximum output voltage to protect the TEC. A voltage from 0 V to 1.5 V applied to the VLIM input to the ADN8830, Pin 15, sets the maximum TEC voltage, VTEC,MAX. This voltage can be set with either a resistor divider or from a DAC. Because the output of the ADN8830 is bi-directional, this voltage sets both the upper and lower limits of the TEC voltage. The equation governing VTEC,MAX is given in equation 15 and the graph of this equation is shown in Fig A10: VTEC , MAX = (1.5 V - VLIM ) x 4
The output voltage across the TEC as measured from Pin 19 to Pin 9 can be monitored at Pin 16. This is labeled as VTEC in the typical application schematic in Figure 1. The voltage at VTEC can vary from 0 V to 3 V independent of the power supply voltage. Its equation is given as: VTEC = 0.25x VOUT _ A -VOUT _ B + 1.5
(
)
(17)
(15)
Where VOUT_A and VOUT_B are the voltages at Pins 19 and 9 respectively. The ripple voltage at pin 19 is filtered out internally and does not appear at VTEC, leaving it as an accurate dc output of the TEC voltage. The TEC is driven with a differential voltage allowing current to flow in either direction through the TEC. This can provide heat transfer either to or from the object being regulated without the use of a negative voltage rail. The maximum output voltage across the TEC is set by the voltage at VLIM, Pin 15. Refer to the Setting the Maximum TEC Voltage section for details on this operation. With VLIM set to ground the maximum output voltage is the power supply voltage, VSY. To achieve a differential output, the ADN8830 has two separate output stages. OUT_A from a switched output, or pulse width modulated (PWM), amplifier and OUT_B is from a high gain linear amplifier. Although they achieve the same result, to pro-
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PRELIMINARY TECHNICAL DATA ADN8830
vide constant voltage and high current, their operations are different. The exact equations for the two outputs are: OUT _ A = 4 x (COMPOUT - 1.5) + OUT _ B OUT _ B = -14 x (COMPOUT - 1.5) + 1.5 (18) (19) achieve the best efficiency. The duty cycle of the PWM sets the OUT_A output voltage and is:
D=
OUT _ A VSY
(21)
Where COMPOUT is the voltage at Pin 13. The voltage at COMPOUT is determined by the compensation network which is fed by the input amplifier, which receives its input voltage from TEMPSET and THERMIN. Equation 19 is only valid in the linear region of the linear amplifier. OUT_B has a lower limit of 0 V and an upper limit of the power supply. Because the COMPOUT voltage is not readily known, equation 19 can be rewritten in terms of the TEC voltage, VTEC which is defined as OUT_B - OUT_A.
OUT _ B = 3.5 x VTEC + 1.5
The average current through the inductor is equal to the TEC current. The ripple current through the inductor, IL, varies with the duty cycle and is equal to:
I L = VSY x D x (1 - D) L x fCLK
(22)
(20)
INDUCTOR CURRENT - A
Referring to Figure 1, Pins 10 and 11 provide the gate drive for Q3 and Q4, which complete the linear output amplifier. This output voltage is fed back to Pin 9, OUT_B, to close its loop. The gate-to-drain capacitance of Q3 and Q4 provide the compensation for the linear amplifier. If using the recommended FDW2520C transistors, it will be necessary to add an additional 2.2 nF of capacitance from the gate to the drain of the PMOS transistor to maintain stability. A 3.3 nF capacitor should also be connected from the drain to ground to prevent small oscillations when there is very little or no current through the TEC. These extra capacitors are specified only when using FDW2520C transistors in the linear amplifier. If other transistors are used, these values may need to be adjusted. To ensure the linear amplifier is stable, the total gate-to-source capacitance for both Q3 and Q4 should be at least 2.5 nF. Refer to the transistor's datasheet for their typical gate-to-drain capacitance values. The output of the linear amplifier is proportional to the voltage at Pin 13, COMPOUT. Because the linear amplifier operates with a gain of 14, its output will typically be at either ground or VSY if there is more than about 100 mA of current flowing through the TEC. This ensures Q3 and Q4 will not be a dominant source of power dissipation at high output currents.
Inductor Selection
Where fCLK is the clock frequency as set by the resistor RFREQ at Pin 26 or an external clock frequency. Refer to the Setting the Switching Frequency section for more information. Selecting a faster switching frequency or a larger value inductor will reduce the ripple current through the inductor. The waveform of the inductor current is shown in Figure 12A.
ITEC
IL
T=
1 fCLK TIME
Figure A12. Current Waveform Through Inductor
In addition to the external transistors, the PWM amplifier requires an inductor and capacitor at its output to filter the switched output waveform. Proper inductor selection is important to
It is important to select an inductor that can tolerate the maximum possible current that could pass through it. Most TECs are specified with a maximum voltage and current for proper and reliable operation. The maximum instantaneous inductor current can be found as:
I L , MAX = ITEC , MAX + 0.5 x I L
(23)
Table II. Partial List of Inductors and Key Specifications
Inductance (H) IMAX (A) 4.7 4.7 4.7 4.7 4.7 4.7 4.7* 10 15 47 1.1 1.59 3.9 1.5 1.32 7.5 5.4 2.7 8 4.5
RS,TYP. (m) 200 55 48 90 56 12 18 80 32 86
Height (mm) 1 2 2.8 3 3 4.5 5.2 2.8 8 7.1
Part Number LPO1704-472M A918CY-4R7M UP2.8B-4R7 DO1608C-472 CDRH4D28 4R7 892NAS-4R7M DO3316P-472 UP2.8B-100 DO5022P-153HC DO5022P-473
Manufacturer Coilcraft Toko Cooper Coilcraft Sumida Toko Coilcraft Cooper Coilcraft Coilcraft
Web site http://www.coilcraft.com http://www.toko.com http://cooperet.com http://www.sumida.com
*Recommend inductor in typical application circuit Figure 1.
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PRELIMINARY TECHNICAL DATA ADN8830
Where IL can be found from equation 22 with the appropriate duty cycle calculated from equation 21 with OUT_A = VTEC,MAX. Design Example 3: A TEC is specified with a maximum current of 1.5 A and maximum voltage of 2.5 V. The ADN8830 will be operating from a 3.3 V supply voltage with a 200 kHz clock and a 4.7 H inductor. The duty cycle of the PWM amplifier at 2.5 V is calculated to be 75.8%. Using equation 22, the inductor ripple current is found to be 664 mA. From equation 23, the maximum inductor current will be 1.82 A and should be considered when selecting the inductor. Notice that increasing the clock frequency to 1 MHz would reduce IL,MAX to 1.56 A. Design Example 4: Using the same TEC as above, the ADN8830 will be powered from 5.0 V instead. Here, the duty cycle is 50%, which happens to be the worst case duty cycle for inductor current ripple. Now, IL equals 1.33 A with a 200 kHz clock, and IL,MAX is 2.83 A. Reducing the inductor ripple current is another compelling reason to operate the ADN8830 from a 3.3 V supply instead. Table 2 lists some inductor manufacturers and part numbers along with some key specifications. The column IMAX refers to the maximum current the inductor is rated at to remain linear. Although higher currents can be pushed through the inductor, efficiency and ripple voltage will be dramatically degraded. This is by no means a complete list of manufacturers or inductors that can be used in the application. More information on these inductors is available at their web sites. Note the trade-offs between inductor height, maximum current, and series resistance. Smaller inductors cannot handle as much current and therefore require higher clock speeds to reduce their ripple current. They also have higher series resistance which can lower the overall efficiency of the ADN8830.
PWM Output Filter Requirements
fC =
1 2
R2 + RL (R1 + RL)C1L1
(24)
Practically speaking, R1 and R2 are several tens of milliohms and are much smaller than the TEC resistance, which can be a few ohms. The cutoff frequency can be roughly approximated as:
fC = 1 1 2 C1L1
(25)
This cutoff frequency should be much lower than the clock frequency to achieve adequate filtering of the switched output waveform. Also of importance is the damping factor of the L-C filter. Too low a damping factor will result in a longer settling time and could potentially cause stability problems for the temperature control loop. Neglecting R1 and R2 again, the damping factor is simply:
=
1 L1 2RL C1
(26)
The switching of Q1 and Q2 creates a pulse-width modulated (PWM) square wave from 0 V to VDD. This square wave must be filtered sufficiently to create a steady voltage that will drive the TEC. The ripple voltage across the TEC is a function of the inductor ripple current, the L-C filter cutoff frequency, and the equivalent series resistance (ESR) of the filter capacitor. The equivalent circuit for the PWM side is given in Figure 13A.
PVDD P1 Q1 R2 L1 RL OUT B N1 Q2 R1 C1 DENOTES PGND OUT A
Using the recommended values of L1 = 4.7 H and C1 = 22 F results in a cutoff frequency of 15.7 kHz. With a TEC resistance of 2 , the damping factor is 0.12. The cutoff frequency can be decreased to lower the output voltage ripple with slower clock frequencies by increasing L1 or C1. Increasing C1 may appear to be a simpler approach as it would not increase the physical size of the inductor, but there is a potential stability danger in lowering the damping factor too far. It is recommended remain greater than 0.05 to provide a reasonable settling time for the TEC. Increasing also makes finding the proper PID compensation easier as there is less ringing in the L-C output filter. To allow adequate phase and gain margin for the PWM amplifier, the following table should be used to find the lower limit of cutoff frequency for a given damping factor.
Table III. Minimum L-C Filter Cutoff Frequency vs. Damping Factor
fC,MIN (kHz) 0.05 0.1 0.2 0.3 0.5 >0.707 8 4 2 1.9 1.6 1.5
Calculating PWM Output Ripple Voltage
Figure A13. Equivalent Circuit for PWM Amplifier and Filter
Although it may seem that fC can be arbitrarily lowered to reduce output ripple, the ripple voltage is also dependent on the ESR of C1, shown as R1 in Figure 12A. This resistance creates a zero which turns the second-order filter into a first-order filter at high frequencies. The location of this zero is: Z1 = 1 2R1C1 (27)
In this circuit, RL is the TEC resistance, R2 is the parasitic resistance of the inductor combined with the equivalent rDS,ON of Q1 and Q2, and R1 is the ESR of C1. The voltage VX is the a pulse width modulated waveform that switches between VSY and ground. This is a second-order low pass filter with an exact cutoff frequency of:
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PRELIMINARY TECHNICAL DATA ADN8830
With a clock frequency greater than Z1, and presumably greater than fC, the output voltage ripple is:
OUT _ A = I L x R1
External FET Requirements
(28)
OUT _ A =
VSY D (1 - D)R1 L1 fCLK
for
( fCLK > Z1)
(29)
The worst-case voltage ripple occurs when the duty cycle of the PWM output is exactly 50%, or when OUT_A = 0.5 VSY. As shown in equation 30:
External FETs are required for both the PWM and linear amplifiers that drive OUT_A and OUT_B from the ADN8830. Although it is important to select FETs that can supply the maximum current required to the TEC, they should also have a low enough resistance (rDS,ON) to prevent excessive power dissipation and improve efficiency. Other key requirements from these FET pairs are slightly different for the PWM and linear outputs. The gate drive outputs for the PWM amplifier at P1 and N1, Pins 21 and 22 respectively, have a typical non-overlap delay of 80 ns. This is done to ensure one FET is completely off before the other FET is turned on preventing current from shooting through both simultaneously. Such shoot-through current could reach in excess of 50 A, which although would only for a brief period, would occur during every switching transition and could quickly burn up the FET pair. The input capacitance (CISS) of the FET should not exceed 6 nF. The P1 and N1 outputs from the ADN8830 have a typical output impedance of 5 . This creates a time constant in combination with CISS of the external FETs equal to 5 CISS. To ensure shoot-through does not occur through these FETs, this time constant should remain less than 30 ns. The linear output from the ADN8830 uses N2 and P2, pins 10 and 11 respectively, to drive the gates of the linear side FETs, shown as Q3 and Q4 in Figure 1A. Local compensation for the linear amplifier is achieved through the gate-to-drain capacitances (CGD) of Q3 and Q4. The value of CGD can be determined from the datasheet as is usually referred to as CRSS, the reverse transfer capacitance. The exact CRSS value should be determined from a graph that shows capacitance versus drain-to-source voltage, using the power supply voltage as the appropriate VDS. To ensure stability of the linear amplifier, the total CGD of the PMOS device, Q3, should be greater than 2.5 nF and the total CGD of the NMOS should be greater than 150 pF. External capacitance can be added around the FET to increase the effective CGD of the transistor. This is the function of C6 in the typical application schematic shown in Figure 1A. If external capacitance must be added, it will generally only be required around the PMOS transistor. In the event of zero output current through the TEC, there will be no current flowing through Q3 and Q4. In this condition,
OUT _ AMAX
VSY R1 4 fCLK L1
for
( fCLK > Z1)
(30)
Here it can be directly seen that increasing the inductor value or clock frequency will reduce the ripple. Choosing a low ESR capacitor will ensure R1 remains low. Operating from a lower supply voltage will also help reduce the output ripple voltage from the L-C filter. With a clock frequency equal to Z1 but presumably greater than fC, the worst-case output voltage ripple is:
OUT _ AMAX = VDD
(16R1 C1 f
2 2
2
CLK
+1
)
32L1C1 fCLK
for ( fCLK = Z 1) (31)
Which, if fCLK < Z1, can be further simplified to:
OUT _ AMAX
VDD 2L1C1 fCLK
2
for
( fCLK < Z1)
(32)
A typical 100 F surface mount electrolytic capacitor can have an ESR of over 100 m, pulling this zero to below 16 kHz, resulting in an excess of ripple voltage across the TEC. Low ESR capacitors such as ceramic or polymer aluminum capacitors are recommended instead. Polymer aluminum capacitors can provide more bulk capacitance per unit area over ceramic ones saving board space. Table IV shows a limited list of capacitors with their equivalent series resistances. This is by no means a complete list of all capacitor manufacturers or capacitors types that can be used in the application. The 22 F capacitor recommended has a maximum ESR of 35 m, which puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended inductor and capacitor listed with a 1 MHz clock frequency will yield a worst-case ripple voltage at OUT_A of about 6 mV.
Table IV. Partial List of Capacitors and Key Specifications
Value (F) 10 22* 22 22 47 68 100
ESR (m) 60 35 35 35 25 18 95
Voltage Rating (V) 6.3 8 8 8 6.3 8 10
Part Number NSP100M6.3D2TR ESRD220M08B NSP220M8D5TR EEFFD0K220R NSP470M6.3D2TR ESRD680M08B 594D107X_010C2T
Manufacturer NIC Components Cornell Dubilier NIC Components Panasonic NIC Components Cornell Dubilier Vishay
Web Site http://www.niccomp.com http://www.cornell-dubilier.com
http://www.maco.panasonic.co.jp
http://www.vishay.com
* Recommend capacitor in typical application circuit Figure 1.
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PRELIMINARY TECHNICAL DATA ADN8830
these FETs will not provide any small signal gain and hence no negative feedback for the linear amplifier. This leaves only a feedforward signal path through CGD, which could cause a settling problem at OUT_B. This is often seen as a small signal oscillation at OUT_B, but only when the TEC is at or very near zero current. The remedy for this potential minor instability is to add additional capacitance from OUT_B to ground. This may need to be determined empirically, but a good starting point is 1.5 times the total CGD. This is the function of C12 in Figure 1A. Note that while adding additional CGD around Q3 and Q4 will help ensure stability, it could potentially increase instability in the zero current dead-band region, requiring additional capacitance from OUT_B to ground. Bear in mind the addition of these capacitors is only for local stabilization. The stability of the entire TEC application may need adjustment, which should be done around the compensation amplifier. This is covered in the Adjusting the Compensation Network section. One additional consideration for selecting both the linear output FETs: They must have a minimum threshold voltage (VT) of 0.6 V. Lower threshold voltages could cause shoot-through current in the linear output transistors. Table V shows the recommended FETs that can be used for the linear output in the ADN8830 application. The table includes the appropriate external gate-to-drain capacitance (Ext. CGD) and snubber capacitor value (CSNUB) connected from OUT_B to ground that should be added to ensure local stability. Table VI shows the recommended PWM output FETs. Although other transistors can be used, these combinations have been tested and are proved stable and reliable for typical applications. Datasheets for these devices can be found at their respective web sites: Fairchild - www.fairchildsemi.com Vishay Siliconix - www.vishay.com International Rectifier - www.irf.com
Calculating Power Dissipation and Efficiency
The total efficiency of the ADN8830 application circuit is simply the ratio of output power to the TEC divided by total power delivered from the supply. The idea in minimizing power dissipation is to avoid both drawing additional power and reducing heat generated from the circuit. The dominant sources of power dissipation will include resistive losses, gate charge loss, core loss from the inductor, and the current used by the ADN8830 itself. The on-channel resistance of both the linear and PWM output FETs will affect efficiency primarily at high output currents. Because the linear amplifier operates in a high gain configuration, it will be at either at ground or VDD when significant current is flowing through the TEC. In this condition, the power dissipation through the linear output FET will be:
PFET , LIN = rDS , ON x ITEC
2
(34)
Using either the rDS,ON for the NMOS or the PMOS depending on the direction of the current flow. In the typical application setup in Figure 1, if the TEC is cooling the target object then the PMOS is sourcing the current. If the TEC is heating the object, the NMOS will be sinking current. Although the FETs that drive OUT_A switch between Q1 and Q2 being on, they have an equivalent series resistance that is equal to a weighted average of their rDS,ON values. REQIV = D x rDS , P1 + (D - 1) x rDS , N 1 (35)
Table V. Recommended FETs for Linear Output Amplifier
Part Number FDW2520C* IRF7401 IRF7233 FDR6674A FDR840P
Type NMOS PMOS NMOS PMOS NMOS PMOS
CGD (nF) 0.17 0.15 0.5 2.2 0.23 0.6
Ext. CGD (nF) - 2.2 - 1.0 - 1.0
CSNUB (nF) - 3.3 - 3.3 - 3.3
rDS,ON (m) 18 35 22 20 9.5 12
IMAX (A) 6.0 4.5 8.7 9.5 11.5 10
Manufacturer Fairchild International Rectifier International Rectifier Fairchild Fairchild
* Recommend transistors in typical application circuit Figure 1.
Table VI. Recommended FETs for PWM Output Amplifier
Part Number FDW2520C* Si7904DN Si7401DN IRF7401 IRF7404
Type NMOS PMOS NMOS PMOS NMOS PMOS
CISS (nF) 1.33 1.33 1.0 3.5 1.6 1.5
rDS,ON (m) 18 35 30 17 22 40
Continuous IMAX (A) 6.0 4.5 5.3 7.3 8.7 6.7
Manufacturer Fairchild Vishay Siliconix Vishay Siliconix International Rectifier International Rectifier
* Recommend transistors in typical application circuit Figure 1.
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PRELIMINARY TECHNICAL DATA ADN8830
The resistive power loss from the PWM transistors is then:
POWER SUPPLY
PFET , PWM = REQIV x ITEC
2
(36)
VDD
GND
There is also a power loss from the continuing charging and discharging of the gate capacitances on Q1 and Q2. The power dissipated due to gate charge loss (PGCL) is: PGCL = 1 2 C ISSVDD fCLK 2 (37)
A V A
ADN8830
V
TEC LOAD
Using the appropriate input capacitance (CISS) for the NMOS and PMOS. Both transistors are switching, so PGCL should be calculated for each one and will be added to find the total power dissipated from the circuit. The series resistance of the inductor, R2 from Figure A13, will also exhibit a power dissipation equal to:
PR2 = R2 x ITEC
2
Figure A14. Measuring Efficiency of the ADN8830 Circuit
(38)
Core loss from the inductor arises as a result of non-idealities of the inductor. Although this is difficult to calculate explicitly, is can be estimated as 80% of PRL at 1 MHz switching frequencies and 50% of PRL at 100 kHz. Judging conservatively:
PLOSS = 0.8 x PRL
The voltmeter to the TEC or output load should include the series ammeter as the power delivered to the ammeter is considered part of the total output power. However, the voltmeter measuring the voltage delivered to the ADN8830 circuit should not include the series ammeter from the power supply. This prevents a false supply voltage power measurement as we are only interested in the supply voltage power delivered to the ADN8830 circuit. Figure A15 and A16 show some efficiency measurements using the typical application circuit shown in Figure A1.
100 VSY = 3V 80
(39)
Finally, the power dissipated by the ADN8830 is equal to the current used by the device multiplied by the supply voltage. Again, this exact equation is difficult to determine as we have already taken into account some of the current while finding the gate charge loss. A reasonable estimate is to use 40 mA as the total current used by the ADN8830. The power dissipated from the device itself is:
PADN 8830 = VDD x 10 mA
EFFICIENCY - %
VSY = 5V 60
40
(40)
20
There are certainly other mechanisms for power dissipation in the circuit, including some external transistor shoot-through current. However, a rough estimate of the total power dissipated can be found by summing the above power dissipation equations. Efficiency is then found by comparing the power dissipated with the required output power to the load.
0 0 500 1,000 ITEC - mA 1,500 2,000
Figure A15. ADN8830 Efficiency with fCLK = 1 MHz
100 VSY = 3V
Efficiency =
Where PLOAD = ILOAD
PLOAD PLOAD + PDISS , TOT
(41)
EFFICIENCY - %
80 VSY = 5V
VLOAD.
60
The measured efficiency of the system will likely be less than the calculated efficiency. Measuring the efficiency of the application circuit is fairly simple but must be done in a exact manner to ensure the correct numbers are being measured. Using two high current, low impedance ammeters and two voltmeters, the circuit should be setup as shown in Figure A14.
40
20
0 0 500 1,000 ITEC - mA 1,500 2,000
Figure A16. ADN8830 Efficiency with fCLK = 200 kHz
Note that higher efficiency can be achieved using a lower supply voltage or a slower clock frequency. This is due to the fact that the dominant source of power dissipation at high clock frequencies is the gate charge loss on the PWM transistors.
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PRELIMINARY TECHNICAL DATA ADN8830
Layout Considerations
The two key considerations for laying out the board for the ADN8830 is to minimize both the series resistance in the output and the potential noise pickup in the precision input section. The best way to accomplish both of these objectives is to divide the layout into two sections, one for the output components and the other for the remainder of the circuit. These sections should have independent power supply and ground current paths which are each connected together at a single point near the power supply. This is used to minimize power supply and ground voltage bounce on the more sensitive input stages to the ADN8830 caused by the switching of the PWM output. Such a layout technique is referred to as a "star" ground and supply connection. Figure A17 shows a block diagram of the concept.
POWER SUPPLY VDD GND
AVDD
AGND NOISE SENSITIVE SECTION
PGND OUTPUT SECTION
PVDD TEC OR LOAD
Figure A18. Top Layer Reference Layout for ADN8830
Figure A17. Using Star Connections to Minimize Noise Pickup from Switched Output
The low noise power and ground are referred to as AVDD and AGND, with the output supply and ground paths labeled PVDD and PGND. These pins are labeled on the ADN8830 and should be connected appropriately. Both sets of external FETs should be connected to PVDD and PGND. All output filtering and PVDD supply bypass capacitors should be connected to PGND. All remaining connections to ground and power supply should be done through AVDD and AGND. A 4-layer board layout is recommended for best performance with split power and ground planes between the top and bottom layers. This provides the lowest impedance for both supply and ground points. Setting the ADN8830 above the AGND plane will reduce the potential noise injection into the device. Figure A18 shows the top layer of the layout used for the ADN8830 demo boards, highlighting the power and ground split planes.
Proper supply voltage bypassing should be taken into consideration as well to minimize the ripple voltage on the power supply. A minimum bypass capacitance of 10 F should be placed in close proximity to each component connected to the power supply. This includes Pins 8 and 20 on the ADN8830 and both external PMOS transistors. An additional 0.1 F capacitor should be placed in parallel to each 10 F cap to provide bypass for high frequency noise. Using a large bulk capacitor, 100 F or greater, in parallel with a low ESR capacitor where AVDD and PVDD connect will further improve voltage supply ripple. This is covered in more detail in the Power Supply Ripple section.
Power Supply Ripple
Minimizing ripple on the power supply voltage can be an important consideration, particularly in signal source laser applications. If the laser diode is operated from the same supply rail as the TEC controller, ripple on the supply voltage could cause inadvertent modulation of the laser frequency. As most laser diodes are driven from a 5 V supply, it is recommended to operate the ADN8830 from a separate 3.3 V regulated supply unless higher TEC voltages are required. Operation from 3.3 V also improves efficiency thus minimizing power dissipation. The power supply ripple is primarily a function of the supply bypass capacitance, also called bulk capacitance, and the inductor ripple current. Similar to the L-C filter at the PWM amplifier output, using more capacitance with low equivalent series resistance (ESR) will lower the supply ripple. A larger inductor value will reduce the inductor ripple current, but this may not be practical in the application. A recommended approach is to use a standard electrolytic capacitor in parallel with a low ESR capacitor. A surface mount 220 F electrolytic in parallel with a 22 F polymer aluminum low ESR cap can occupy an approximate total board area only of 0.94 square inches or 61 square millimeters. Using these capacitors along with a 4.7 H inductor can yield a supply ripple of less than 5 mV. High frequency transient spikes may appear on the supply voltage as well. This is due to the fast switching times on the PWM transistors and the sharp edges of their gate voltages. Although these transient spikes can reach several tens of millivolts at their peak, they typically last for less than 20 ns and have a resonance greater than 100 MHz. Additional bulk capacitance will not
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PRELIMINARY TECHNICAL DATA ADN8830
appreciably affect the level of these spikes as such capacitance is not reactive at these frequencies. Adding 0.01 F ceramic capacitors on the supply line near the PWM PMOS transistor can reduce this switching noise. Inserting an RF inductor with a high-Q around 100 MHz in series with PVDD will also block this noise from traveling back to the power supply.
Setting Maximum Output Current and Short Circuit Protection
Although the maximum output voltage can be programmed through VLIM to protect the TEC from overvoltage damage, the user may wish to protect the ADN8830 circuit from a possible short circuit at the output. Such a short could quickly damage the external FETs or even the power supply as they would attempt to drive excessive current. Figure A19 shows a simple modification that will protect the system from an output short circuit.
VSY TO FETS RS 10m PVDD AVDD
This leaves Q1 on, effectively connecting D1 to the positive rail and leaving the voltage on C1 at VDD. Should enough current flow through RS to drop VS below VX, Q1 will turn off and C1 will discharge through R2 down to a logic low to activates the ADN8830 shutdown. Once VS returns to a voltage greater than VX, Q1 will turn back on and C1 will charge back to VDD through R1. The shutdown and re-activation time constants are approximately: SD = C1 x R1 ON = C1 x R1 (42)
The shutdown time constant should be a minimum of ten clock cycles to ensure high current switching transients do not trigger a false activation. If powered from 5 V, the circuit shown will shutdown the ADN8830 should PVDD deliver over 5 A for more than 1 ms. After shutdown, the circuit will reactivate the ADN8830 in about 1 second. The current from the power supply and through the shunt resistor is less than the current delivered to the load due to the efficiency of the PWM amplifier. The voltage drop across RS is found as:
PVDD R3 1k Q1 FDV304P OR EQUIV. R2 1k D1 MA116CT-ND OR EQUIV. R1 1M SD C1 1F
AD8601
R4 100k VX
VRS =
IOUT RLRS VDD
2
DENOTES AGND
DENOTES PGND
Figure 19. Implementing Output Short Circuit Protection
A 10 m resistor placed in series with the PVDD supply line creates a voltage drop proportional to the absolute value of the output current. The AD8601 is a CMOS amplifier that is configured as a comparator. As long as the voltage at its inverting input (VS) exceeds the voltage set by the resistor divider at the non-inverting input (VX), the gate of Q1 will remain at ground.
+5V IOUTA
Where RL is the load resistance or resistance of the TEC and is the efficiency of the system. An estimate of efficiency can either calculated from the Calculating Power Dissipation and Efficiency section or from figures A15 and A16. A reasonable approximation is = 0.85. Although the exact resistance of a TEC varies with temperature, an estimation can be made by dividing the maximum voltage rating of the TEC by its maximum current rating. In addition to providing protection against a short at the output, this circuit will also protect the FETs against shoot-thru current. Shoot-through will not occur when using the recommended transistors and additional capacitance shown in Tables 5 and 6.
ADT70
IOUTB
+INOA R3 82.5 TO THERM_IN = 1V @ 25 C OUTOA +INIA RGA R3 82.5 4.99k RGB 25mV/ C
INST AMP
-INIA RTD 1k R3 1k GND SENSE AGND OUTIA 1k -INOA 5.11k
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure A20. Using an RTD for Temperature Feedback to the ADN8830
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PRELIMINARY TECHNICAL DATA ADN8830
However, if different transistors are used where their shootthrough potential is unknown, implementing the short circuit protection circuit will unconditionally protect these transistors. To set a maximum output current limit, use the circuit in Figure A25. This circuit can share the 10 m power supply shunt resistor as the short-circuit protection circuit to sense the output current. In normal operation Q1 is on, pulling the ADN8830 VLIM pin down to the voltage set by VLIMIT. This sets the maximum output voltage limit as described in the Setting the Maximum TEC Voltage section.
VSY TO FETS RS 10m PVDD AVDD R1 3.48k Q1 FDV301N OR EQUIV. C1 1nF
TO TEC
RS 10m
AVDD TO OUT B AVDD 200k VHI 1nF 300k
8
AVDD
AVDD R1 3.48k
IL
TO VLIM R2 1.47k
AD8626
VX
AD8602
Q1,Q2 FDG6303N OR EQUIV.
300k
TO VREF
TO VLIM
VLO 200k
VLIMIT (0V TO 1.5V)
PVDD R3 178
R2 1.47k
Figure 26: A High Accuracy Output Current Limit
AD8605
R4 100k VX
VLIMIT (0V TO 1.5V) DENOTES AGND DENOTES PGND
The upper and lower trip point voltages can be set independently allowing different maximum output current limits depending on the direction of the current. The resistor divider for VHI and VLO is tapped to VREF to maintain window accuracy with any changes in VREF. Using the values from Figure A26 with a 5 V supply, the output current will not exceed 1.5 A in either direction. Adding the current sensing resistor will slightly reduce efficiency. The power dissipated by this resistor is equal to ITEC2 x RS, and should be included when calculating efficiency as described in the section titled Calculating Power Dissipation and Efficiency.
Using an RTD for Temperature Sensing
Figure A25. Setting a Maximum Output Current Limit
If the voltage at VSY drops below VX, then Q1 is turned off and the VLIM pin will be set to 1.5 V, effectively setting the maximum voltage across the outputs to 0 V. The voltage divider for VX is calculated from Equation 43.
Design Example 5
A maximum output current limit needs to be set at 1.5 A for a TEC with a maximum voltage rating of 2.5 V. The ADN8830 is powered from 5 V. The TEC resistance is estimated at 1.67 and efficiency at 85%. Using Equation 43, the voltage drop across RS will be 8.8 mV when 1.5 A is delivered to the TEC. The trip voltage VX is set to 4.991 V with R3 = 178 and R4 = 100 k as shown in Figure A25. To set the output voltage limit to 2.5 V, the voltage at VLIMIT should be set to 0.875 V according to Equation 15. The C1 capacitor is added to smooth the voltage transitions at VLIM. Once an over-current condition is detected, the output voltage will turn down to 0 V within 30 ms. For a more exact measurement of the output current, place a sense resistor in series with the output load as shown in Figure A26. The AD626 instrumentation amplifier is set for a gain of 100 with a reference voltage of 2.47 V from VREF. The output of the AD626 is equal to 100 x RS x IL and is fed to the AD8602 which is set up as a window comparator. With VX greater than VLO but less than VHI, VLIM will be pulled down to the voltage at VLIMIT. Should VX fall outside the voltage window, VLIM will be pulled to 1.5 V as in Figure A25. The trip points should be set according to: VHI = VREF + 100 x RS I LIMIT + VLO = VREF - 100 x RS I LIMIT -
The ADN8830 can be used with a resistive-temperature device (RTD) as the temperature feedback sensor. The resistance of an RTD is linear with respect to temperature, offering an advantage over thermistors which have an exponential relationship to temperature. A constant current applied through an RTD will yield a voltage proportional to temperature. However, this voltage could be on the order of only 0.5 mV per C, thus requiring the use of additional amplification to achieve a usable signal level. The ADT70 from Analog Devices can be used to bias and amplify the voltage across an RTD, which can then be fed directly to the THERM_IN pin on the ADN8830 to provide temperature feedback for the TEC controller. The ADT70 uses a 0.9 mA current source to drive the RTD and an instrumentation amplifier with adjustable gain to boost the RTD voltage. Application notes and typical schematics for this device can be found in the ADT70 datasheet. Most RTDs have a positive temperature coefficient, also called tempco, as opposed to thermistors which have a negative tempco. For the OUT_A output to drive the TEC- input as shown in Figure 1A, the signal from an RTD must be conditioned to create a negative tempco. This can be easily done using an inverting amplifier. Alternately, OUT_A can be connected to drive TEC+ with OUT_B driving TEC- with a positive tempco at THERMIN. This is highlighted in the Output Driver Amplifiers section. For ADN8830 proper operation care should be taken to ensure the voltage at THERMIN remain within 0.4 V and 2.0 V. Using a 1 k RTD with the ADT70 will yield a THERMIN voltage of 0.9 V at 25C. Using the application circuit shown in Figure A20 will provide a nominal output voltage of 1.0 V at 25C and a total gain of 66.7 mV/. Using an RTD with a temperature coefficient of 0.375 /C will give a THERMIN voltage swing from 1.5 V at 5C to 0.5 V at 45C, well within the input range of the ADN8830. -19-
(44)
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PRELIMINARY TECHNICAL DATA ADN8830
Using a Resistive Load as a Heating Element
VPWR
The ADN8830 can be used in applications that do not necessarily drive a TEC, but require only a high current output into a load resistance. Such applications generally only require heating above ambient temperature only and simply use the power dissipated by the load element to accomplish this. Because the power dissipated by such an element is proportional to the square of the output voltage, the ADN8830 application circuit must be modified. Figure A21 shows the preferred method for driving a heating element load.
PVDD P1 Q1 L1 RL OUT B OUT A
Q3 MAT-03 I1 R1 10k
Q4 MAT-03 Q1 FDR840P
+5V
VX R2 10k
20 PVDD P1 11
TO TEC+
P1 P1
10 23 383k
Q2 FDR6674A
OUT B N1 Q2 C1 Q3 N2
9
ADN8830
NOTE: NO CONNECTION TO P2 REQUIRED
1nF
Figure A23. Boosting Linear Output Voltage up to 14 V Figure A21. Using the ADN8830 to Drive a Heating Element
Current is delivered from the PWM amplifier through Q3 when the voltage at THERMIN is lower than TEMPSET. If the object temperature is greater than the target temperature, Q3 will turn off and the current through the load goes to zero, allowing the object to cool back towards the ambient temperature. As the target temperature is approached, a steady output current should be reached. Naturally, a proper compensation network must be found to ensure stability and adequate temperature settling time. The P2 output from the ADN8830 should be left unconnected.
Boosting the Output Voltage
Note that both external FETs on the outputs of the ADP3414 must be NMOS. A PMOS transistor cannot be substituted when using this voltage boosting circuit. Larger transistors may be required to handle higher output currents to the TEC or heating element. The ADP3414 ensures one FET is completely off before turning the other FET on, thereby protecting against possible shoot through current. The P1 output from the ADN8830 is inverted using a high speed CMOS logic gate, providing the input signal to the ADP3414. The N1 output can be left with no connection. The L-C filter can be calculated as described in the PWM Output Filter Requirements section. A 402 k feedback resistor must be placed in series to the OUT_A input to ensure the voltage at Pin 19 does not exceed 5 V. The maximum output voltage to the load can still be limited by the VLIM pin on the ADN8830. The limited boosted differential output voltage is set as: VOUT , MAX = 4 x VPWR x (1.5 - VLIM ) VDD (43)
Although the ADN8830 is designed for operation only up to 5 V, the output circuit can be modified to boost the output voltage up to 14 V. This may be required for higher voltage TECs or when more current is required from a resistive heating element. Additional circuitry is required to increase the gate drive voltage to the PMOS transistors. Figure A22 shows the modification for the PWM output. The ADP3414 takes a 0 V to 3 V input signal and converts it to the appropriate levels for both the external FETs.
+5V 4 VCC +5V +5V 20 PVDD P1 2 21 N1 PGND 23 OUT A 19 22 IN
D1 MBR052LTI VPWR BST 1 1F Q1 FDB7030L TO TEC- L1 DRVL 5 C1 Q2 FDB8030L
DRVH
8
ADN8830
SW
7
74HC04
PGND
6
ADP3414
402k
NOTE: NO CONNECTION TO N1 REQUIRED
Figure A22. Boost PWM Output Voltage up to 14 V
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PRELIMINARY TECHNICAL DATA ADN8830
To set the maximum output voltage to 10 V with VPWR = 12 V and PVDD = 5 V, VLIM should be set to 0.46 V. The input signal to the ADP3414 should never reach 100% duty cycle or the device will not operate properly. To prevent the ADN8830 P1 output from reaching a 100% duty cycle, the VLIM voltage pin should be set according to Equation 15, or Figure A10, to ensure VTEC,MAX is less than PVDD. For example: With PVDD = 5 V, VLIM must be set to a minimum of 0.25 V for the boosting circuit to operate correctly. Additional applications information on the ADP3414 can be found on the Analog Devices website at www.analog.com. No modification is required to the external NMOS FET connected to N2 for the linear amplifier output. If the output load is a resistive heating element, then do not connect a PMOS transistor to the P2 output from the ADN8830 as shown in Figure A21. If the load is a TEC, then connect the PMOS as shown in Figure A23. Here, a voltage level shift must be added to provide the correct gate drive voltage for Q1. This is done by using a current mirror where I1 sets up the reference current and I2 equals I1. The voltage at VX will be approximately:
VX VP1 + VPWR - VDD - VBE , Q 3
(44)
Where VP1 is the output voltage at P1. The typical VBE for the MAT03 will a collector current of 840 mA is about 0.58 V. Using the supply voltages as shown in Figure A23,
VX VP1 + 8.42 V
(45)
When P1 is driven low the gate-to-source voltage of Q1 is about 5.58 V, which is enough to turn Q1 on in a low-resistance state. When the P1 output goes high to 5 V, VGS of Q1 is approximately 0.58 V, the VBE drop across Q3. This turns Q1 off. Other bipolar transistors and PMOS FETs can be used provided the threshold voltage (VT) for Q1 is higher than the VBE drop across Q1. Otherwise, Q1 will never fully turn off and excessive shoot-thru current could occur through Q1 and Q2. A feedback resistor between TEC+ and OUT_B of 383 k must be used to prevent more than 5 V from reaching OUT_B. A 1 nF capacitor is placed in parallel to improve the linear amplifier stability and loop response time. Although these voltage boosting circuits can be used with lower voltages, VPWR cannot exceed 14 V for both the linear and the PWM boosting circuits.
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PRELIMINARY TECHNICAL DATA ADN8830
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
32-Lead LFCSP (CP Suffix)
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 25 0.009 (0.24) 24
0.197 (5.0) BSC SQ
0.010 (0.25) MIN
32
1
PIN 1 INDICATOR
TOP VIEW
0.187 (4.75) BSC SQ
0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30)
17 16
BOTTOM VIEW
0.128 (3.25) 0.122 (3.10) SQ 0.116 (2.95)
98
12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE
0.031 (0.80) MAX 0.026 (0.65) NOM
0.138 (3.50) REF
0.002 (0.05) 0.0004 (0.01) 0.020 (0.50) 0.008 (0.20) 0.0 (0.00) BSC REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2
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